Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.
As a member of Microchip’s engineering community, your primary responsibility will be to design, simulate, and verify the SI/PI (Signal Integrity and Power Integrity) solution for an advanced FPGA device together with its package and board components. This includes power supply modeling and ripple analysis and methods to control and reduce ripple by means of die/package/board de-coupling. Also includes detailed modeling and analysis and reduction of clock jitter for internal system clocks of the FPGA as well as for high speed clocks employed for 3.2Gbs DDR Memory interfaces.
FPGA is a complex System On-Chip containing multiple power supplies, ASIC logic blocks, custom circuit blocks, and three types of high speed, programmable IO buffers. As a secondary assignment, you will contribute to the development of area and low power optimized, 3V programmable FPGA IO used in a variety of IO interfaces and supporting a variety of drive strengths and input/output modes.
Duties & Responsibilities
- Develop overall plan for implementing low supply ripple and noise coupling across a wide frequency range for die/package/board PDN distribution network.
- Extract (ANSYS HFSS plus Calibre) and model complete die/package/board system in SPICE.
- Simulate and confirm all critical operating parameters: AC sweeps for minimum PDN impedance, identify resonance peaks and optimization of all RLC components in system.
- Package substrate cap analysis with substrate inductance minimization and added dampening resistance for
- optimal noise and jitter reduction with lowest resonance peak.
- Perform board de-coupling analysis for optimal noise reduction using fewest number of board caps for
- customer cost and board area advantage.
- Develop and utilize on-die de-coupling for optimal noise and jitter reduction for system clocks and high
- speed IO interface clocks. Local IR drop and self-heating effects must be included as part of the analysis.
- Achieve very low jitter target for Ref_Clk outputs on DDR Memory Interfaces. Effectively and accurately
- model, simulate and predict clock jitter behavior to meet design targets.
- Develop extraction method to model core VDD capacitance and develop comprehensive core noise model to
- accurately predict via simulation system clock jitter and inter-domain clock jitter.
- Evaluate supply topology choices of limited supply isolation vs. a common supply to optimize jitter.
- Develop schematics; verify S-param models, extraction flows, and build SPICE decks and simulate.
- Maintain comprehensive presentations to capture work progress and for Design Reviews.
- Work with 3rd Party CAD vendors and AE’s as needed to bring up tools and debug issues.
- Support derivative product/package products (4 to 5 die size variants with 2 to 4 packages per device).
- Provide support for design, layout, test, and characterization teams.
IO Buffer Design and Development –
This is a secondary job function with SI/PI being primary. Entails some or all the following:
- Design and develop low area, low power, high feature set 3V FPGA IO buffer operating from 3.3V down to 1.2V including:
- Single ended and differential receivers.
- Voltage domain translators.
- Programmable for drive strength, mode, output voltage, input ODT termination value.
- Write specification for 3V IO Buffer. Provide customer Datasheet specifications.
- Simulate AC paths, DC drive limits, and perform functional verification.
- Create detailed Design Review document.
- Support verification staff and timing characterization team.
- Bachelors/Master’s in Electrical Engineering, Physics, Computer Engineering or Computer Science.
- Minimum of 10 years of proven silicon design experience including some combination of: modeling and simulation of die/package/board for SI and PI effects of large complex die for minimum clock jitter; and/or high speed, low power, custom design experience with proven development in either analog circuits or IO buffer circuit design.
- Minimum of several successful previous custom circuit developments.
- High degree of SPICE simulation proficiency.
- Demonstrated competency in scripting, managing simulation queues, and data capture plus presentation using Microsoft Office tools, including Excel.
- Ability to support layout, verification, or timing characterization teams.
- Ability to extract and simulate board and package S-param models of signal traces and PDN.
- Knowledge of on-die signal integrity parameters, noise/coupling mechanisms and sources, and the means to control and reduce on-die clock jitter.
- Cadence Composer schematic entry. Full custom design tool set.
- Good analytical, oral and written communication skills
- Able to write clean, readable presentations.
- Self-motivated, proactive team player.
- Ability to work to schedule requirements.
- Analog and full custom design experience.
- Experience in FPGA or ASIC development and full chip integration.